The present invention relates generally to digital data communication, and more particularly to an interface for use in facilitating data communication between a computer and a plurality of peripherals.
To increase the utility of digital computers it has become a common practice to connect a central computer to a series of peripherals or attachments, which are typically located remote from the computer in a network configuration. The peripherals are typically a printer, a terminal, a personal computer (PC) and the like, and each includes its own microprocessor. In order for these peripherals to operate, each must be able to communicate with the central computer in accordance with a common data protocol or format established by the computer.
In order for the computer to be able to communicate selectively with the peripherals, each of the peripherals is typically assigned a unique address. Each data stream or message from the computer includes, along with the data directed to the peripheral and sync and parity bits, the address for the peripheral to which the message is intended. After the peripheral has processed or acted on the data transmitted to it in this fashion, the peripheral returns a message to the computer, which includes the address of the peripheral from which the message emanates along with appropriate data and synchronization bits.
To allow the computer to communicate with the peripheral an interface is typically provided for each peripheral to convert the message format received from the computer to a format that can be processed in the peripheral microprocessor. In the known computer peripheral interfaces, the address of the first message frame that is received from the computer is checked to determine if the message is directed to that peripheral; that is, if the address portion of the received message is that of the peripheral. In those cases in which a particular peripheral must respond to (or emulate) multiple addresses, the interface must check the received addresses to all the possible peripheral addresses (typically up to seven). This process requires a not insignificant time.
Moreover, after the conventional attachment determines that the message from the computer is intended for it, and that the peripheral must then respond to the computer, it must provide two bytes of information for every outgoing frame--one byte for data and the second byte for the peripheral address. This is a disadvantage because the microprocessor associated with that peripheral has to save and reproduce the address and perform two write operations for every outgoing frame.
In addition, if the frame of the message from the addressed peripheral to the computer is the last frame in a multi-frame message, the microprocessor in the conventional interface must keep track of the data it is sending to determine that it is sending the last frame, and, instead of sending the peripheral address information it must send the end-of-message delimiter (typically a three-bit address of binary 111 or seven).
In large part owing to these requirements, the conventional peripheral interface circuits have been bulky and expensive, typically consisting of as many as 100 integrated circuits mounted on a board. There is thus a present need for a less expensive and less bulky interface for use in connecting a plurality of different peripherals to a central computer and which still allows the logic of the peripheral to conform to the protocol of the computer.
It is accordingly an object of the present invention to provide an interface of the type described which is less costly and less complex than the presently known peripheral interface circuits.
It is another object of the invention to provide a peripheral interface of the type described which facilitates and speeds up data communication between a peripheral and a computer.
It is a further object of the invention to provide a peripheral interface of the type described which can function with a less complex and thus less expensive microprocessor.
It is yet a further object of the present invention to provide a peripheral interface of the type described which can be used to respond to a plurality of peripheral addresses.
To these ends, the peripheral interface of the invention includes means for stripping the address bit from the message received from the computer and for comparing the stripped address with its own address. The stripped message is saved and returned to the computer as part of a return message only if there has been a match detected between the received address and the address (or one of the addresses) of the peripheral.